IBM memory breakthrough could dramatically increase performance and capacity

IBM revisits 50-year-old technology to boost memory capacity and performance

IBM is claiming a "breakthrough" in memory technology that, it claims, could increase memory capacity at a lower cost than current DRAM technologies.

According to IBM, it has found a way to put three bits of data per cell by revisiting a 50-year-old technology called phase change memory (PCM).

Unlike standard DRAM, which can manage around 3,000 write cycles, PCM can cope with at least 10 million, meaning that its durability in the constant write and rewrite of data centres and advanced computers shouldn't be a problem. It is also non-volatile, meaning that it does not need a power supply to retain information.

PCM renders itself in two states - amorphous and crystalline - acting as flags for zeroes and ones. A medium electrical current sets the state, while a low current reads it back.

IBM is looking to create hybrid devices offering PCM and flash, with PCM acting as a cache that could, for example, accelerate device boot.

Rolled out at a grander level, the blazing fast retrieval could give organisations a huge edge when dealing with financial transactions, for example, or conducting real-time analytics.

Up until now, scientists had managed to store only one bit per cell, but at the IEEE International Memory Workshop in Paris this week, the IBM team demonstrated storing three bits per cell in a 64k cell array at elevated temperatures after a million endurance cycles.

In other words, they've achieved a way of doing it reliably over and over again. The key is non-volatility and some new advances in preventing 'drift' of cell state, and that's exactly what the team has achieved.

The experimental PCM chip was connected to a standard integrated circuit board with a 2x2 Mcell array with a four-bank interleaved architecture. The memory array size is 2 x 1000 micrometres by 800 micrometres. The cells are based on doped-chalcogenide allowing them to be integrated into the chip as a characterisation in 90nm CMOS baseline technology.

"Combined, these advances address the key challenges of multi-bit PCM, including drift, variability, temperature sensitivity and endurance cycling," said IBM Fellow Dr Evangelos Eleftheriou.